Whats wrong in the following module ?
module bus_16bit(bus , sel , Mem_In , AR_In , PC_In , DR_In , AC_In , IR_In);
output [15:0] bus;
input [15:0] IR_In, DR_In, Mem_In, AC_In;
input [11:0] PC_In, AR_In;
input [2:0] sel;
reg [15:0] out;
always @(sel) begin
case(sel)
3'b001 : bus = {4'b0000,AR_In};
3'b010 : bus = {4'b0000,PC_In};
3'b011 : bus = DR_In;
3'b100 : bus = AC_In;
3'b101 : bus = IR_In;
3'b111 : bus = Mem_In;
default : bus = 16'b0;
endcase
end
endmodule
The errors i get upon compilation are…
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
“data_unit.v”, 139: bus = {4’b0, AR_In};
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
“data_unit.v”, 140: bus = {4’b0, PC_In};
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
“data_unit.v”, 141: bus = DR_In;
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
“data_unit.v”, 142: bus = AC_In;
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
“data_unit.v”, 143: bus = IR_In;
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
“data_unit.v”, 144: bus = Mem_In;
Error! Illegal left-hand-side assignment [Verilog-ILHSA]
“data_unit.v”, 145: bus = 16’b0;